IEEE

Case Study: Optimization Methods With TVM Hybrid-OP on RISC-V Packed SIMD

Abstract: In recent years, considerable research has focused on the use of custom hardware to accelerate deep learning on edge devices. However, the end-to-end flow of deep learning includes ...
IEEE

Venus: A RISC-V Domain Specific Architecture Towards Integrated AI and Wireless Baseband Processing for 6G Edge Intelligence

Abstract: Future 6G local area networks (LANs) are expected to inherently feature edge artificial intelligence (AI) capabilities, despite constraints on power consumption and device dimensions.
Semiconductor Engineering

Managing Complexity: Evolving Approaches To Design Rule Checking In Modern IC Design

Why it's essential to combine sign-off accuracy, iterative feedback, and intelligent automation in complex designs.
GitHub

SGDH-RVSoC Project, a portable and Linux capable RISC-V computer system on an FPGA

The RVSoC Project was the origin, serving as a research and development project of the RISC-V computer system targeting FPGAs in Verilog HDL at Arch Lab, Tokyo Tech. Building on this foundation, we ...
theregister

Qualcomm takes RISC on Arm alternative with Ventana acquisition

Qualcomm could soon be serving up RISC-V cores alongside its custom Arm ones following the acquisition of Ventana Micro Systems on Wednesday. Founded in 2018, Ventana has developed several generations ...
Design-Reuse

RISC-V: The Open-Source Revolution in CPU Architecture

RISC-V is an open-source Instruction Set Architecture (ISA) that rapidly transforms the CPU design and development landscape. Unlike proprietary ISAs, RISC-V allows free access to architecture ...